`timescale 1ns / 1ps

module display_driver_sim();
    reg clk = 1'b0;
    reg [7:0] display_en = 8'b1111_1111;
    reg [23:0] display_num = 24'o1234_5670;
    reg [7:0] display_extra = 8'b0000_0000;
    reg [2:0] display_blink = 3'b000;
    wire [7:0] high_bus;
    wire [7:0] low_bus;
    wire [7:0] display_en_o;

    display_driver UUT(
        clk,
        display_en,
        display_num,
        display_extra,
        display_blink,

        high_bus,
        low_bus,
        display_en_o
    );

    always #1 begin clk = ~clk; end

    initial begin
        // DISPLAY 8_BIT OCTAL NUMBER
        begin
            display_en <= 8'b1111_1111;
            display_num <= 24'o01234567;
            display_extra <= 8'b0000_0000;
            display_blink <= 3'b000;
        end
        #40
        begin
            display_en <= 8'b1111_1111;
            display_num <= 24'o01234567;
            display_extra <= 8'b1111_1111;
            display_blink <= 3'b000;
        end
        #40
        begin
            display_en <= 8'b0001_1111;
        end
        #40
        begin
            display_en <= 8'b1111_1111;
            display_blink <= 3'b100;
        end
        #1000
        begin
            display_blink <= 3'b010;
        end
        #2100 $stop;
    end
endmodule
